Sharp ER-87SL Manuel de service Page 24

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Pin
NO.
Name ER-A770 I/O Description
142 VCC VCC +5V
143 GND GND GND
144 /CSD VCC IS +5V
145 TRNDTD NC O NC
146 /DTRD NC O NC
147 /RTSD NC O NC
148 RCVDTD GND IS GND
149 /CTSD GND IS GND
150 /DSRD GND IS GND
151 TRNRDYD NC O NC
152 RCVRDYD NC O NC
153 TRNEMPD NC O NC
154 SYCBKD NC IO NC
155 /WIN /WRH I Write signal
156 /RIN /RDH I Read signal
157 RSLCT0 AH0 I Address bus
158 RSLCT1 AH1 I Address bus
159 RST RES USART IS Reset signal
160 MCLK CLK USART I Clock (4.91MHz)
I TTL input
ID TTL input with pull down
IS TTL Schmidt input
ISU TTL Schmidt input with pull up
IO TTL I/O
3S 3-state Buffer (6mA)
ON6 Open drain (6mA)
3. Clock generator
1) CPU (HD64151010FX)
Fig. 3-1
Basic clock is supplied from a 19.66 MHz ceramic oscillator.
The CPU contains an oscillation circuit from which the basic clock is
internally driven. If the CPU was not operating properly, the signal
does not appear on this line in most cases.
2) CKDC8 oscillation circuit
Fig. 3-2
Two oscillators are connected to the CKDC8.
The main clock X1 generates 4.19MHz which is used during power
on.
When power is turned off, the CKDC8 goes into the standby mode
and the main clock stops.
The sub-clock X2 generates 32.768KHz which is primarily used to
update the internal RTC (real time clock). During the standby mode, it
keeps oscillating to update the clock and monitoring the power recov-
ery.
4. Reset (POFF) circuit
Fig. 4-1
In order to prevent memory loss at a time of power off and power
supply failure of the ECR, the power supply condition is monitored at
all times. When a power failure is met, the CPU suspends the execu-
tion of the current program and immediately executes the power-off
program to save the data in the CPU registers in the external S-RAM
with the signal
STOP forced low to prepare for the power-off situation.
The signal
STOP is supplied to the CKDC8 as signal RESET to reset
the devices.
This circuit monitors +24V supply voltage.
CPU
(HD64151010FX)
99
98
XTAL
EXTAL
19.66MHz
X4
101
PHAI
37
38
33P
HD404728A91FS
C105
CKDC 8
X2
X1
4.19MHz
X2
32.768KHz
2
1
3
41
18P
C106
40
X1
XT2
XT1
R164
330K
+
-
/POFF
3
2
1
4
8
B
IC7A
KIA393F
C37
1000P
D7
1SS133
C83
1µ 50V
+
ZD2
MTZ5.1A
R116
9.1KG
R115
15KG
R118
56K
R117
2.7K
R119
2.7K
R114
8.2KG
+24V +5V
POFF
CPU
72
IRQ0
89
RESET (FROM CKDC 8)
STOP (TO CKDC 8)
MPCA7
13 48
1
IRQ0
54
INT0
4 – 16
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