Sharp UP-700 Manuel de service télécharger pdf (Page 50)

• Phase calculation mode

– 2-phase encoder calculation processing

Compare Match Timer (CMT) (Two Channels):

• 16-bit free-running counter

• One compare register

• Generates an interrupt request upon compare match

Watchdog Timer (WDT) (One Channel):

• Watchdog timer or interval timer

• Count overflow can generate an internal reset, external signal, or

interrupt

Serial Communication Interface (SCI) (Two Channels):

(Per Channel):

• Asynchronous or clock-synchronous mode is selectable

• Can transmit and receive simultaneously (full duplex)

• On-chip dedicated baud rate generator

• Multiprocessor communication function

I/O Ports:

• SH7014

– Input/output: 35

– Input: 8

– Total: 43

A/D Converter:

• 10 bits 8 channels

• The SH7014 has a high-speed A/D converter.

On-Chip Memory:

• ROM

– SH7014: ROMless

• RAM: SH7014: 3 kbytes (1 kbyte when cache is used)

Operating Modes:

• Operating modes

– Non-extended ROM mode

• Processing states

– Program execution state

– Exception processing state

• Power-down modes

– Sleep mode

– Software standby mode

Clock Pulse Generator (CPG):

• On-chip clock pulse generator

– On-chip clock-doubling PLL circuit

1)-2. Block Diagram

Figure 1. is a block diagram of the SH7014.

1)-3. Pin Arrangement and Pin Functions

1)-3-1. Pin Arrangment

Figure 2. shows the pin arrangement for the SH7014 (top view).

A15

A14

A13

A12

A11

A10

D15

D14

D13

D12

D11

D10

MD3

MD2

MD1

MD0

NMI

EXTAL

XTAL

PLLVCC

PLLCAP

PLLVSS

RES

WDTOVR

PB9/IRQ7/A21

PB8/IRQ6/A20/WAIT

PB7/A19

PB6/A18

PB5/IRQ3/RDWR

PB4/IRQ2/CASH

PB3/IRQ1/CASL

PB2/IRQ0/RAS

A17

A16

PA15/CK

WRH

WRL

CS1

CS0

PA9/TCLKD/IRQ3

PA8/TCLKC/IRQ2

PA7/TCLKB/CS3

PA6/TCLKA/CS2

PA5/SCK1/DREQ1/IRQ1

PA4/TXD1

PA3/RXD1

PA2/SCK0/DREQ0/IRQ0

PA1/TXD0

PA0/RXD0

PE15/DACK1

PE14/DACK0/AH

PE13

PE12

PE11

PE10

PE9

PE8

PE7/TIOC2B

PE6/TIOC2A

PE5/TIOC1B

PE4/TIOC1A

PE3/TIOC0D/DRAK1

PE2/TIOC0C/DREQ1

PE1/TIOC0B/DRAK0

PE0/TIOC0A/DREQ0

: Peripheral address bus

: Peripheral data bus

: Internal address bus

: Internal upper data bus

: Internal lower data bus

PLL

PF7/AN7

PF6/AN6

PF5/AN5

PF4/AN4

PF3/AN3

PF2/AN2

PF1/AN1

PF0/AN0

RAM (3 kB)/

cache (1 kB)

CPU

Direct memory

access controller

Interrupt

controller

Bus state controller

Serial communi-

cation interface

(• 2 channels)

Multifunction timer/

pulse unit

Compare match

timer (• 2 channels)

A/D

converter

Watch-

dog

timer

Figure 1. Block Diagram of the SH7014

PB13